Simulating a 12V 4S3P Lithium Battery & Wiring Strategies

Now that we have an LTSpice model for an LF280 LiFePo4 280AH cell and for the pack's wiring interconnects, let's move on to this van's 12V working voltage, with the 4S3P 'Summer' pack.

More simulations, yay !

As a start, we'll use the excellent 0.15mΩ cell-terminal-to-cell-terminal jumper setup for the Rs series interconnects that uses two 4 AWG wires in parallel. Same for the Rp main parallel interconnects where the main wiring connects to the pack:

Opposite corners wiring topology:

R1s = open

Max string and cell current = 54A, Min = 46A
Settling time: 3 hours

Looks good. With that we can now study the impact of R1s (1S pool interconnects). Those are usually much thinner than the main interconnects, so let's assume 0.4mΩ as a start:

R1s = 0.4mΩ

Max= 76A, Min= 32A
Settling time: over 6 hours

Zoink ! Creating a matrix interconnect topology actually increased the imbalance quite a bit.

Let's see what happens if R1s is upgraded to 0.15mΩ:

R1s = 0.15mΩ

Max= 83A, Min= 28A
Settling time: 4.7 hours

As expected, the current imbalance got worse. What is happening is that the cells closest to the main wiring in the corners experience more current. Because the 1S interconnects now provide current paths for most of the other cells to also reach the main wiring's pick up points via those corner cells. If that makes sense ?

Conclusion: in the opposite corners topology the larger the gauge of the 1S pool wires the more current imbalance.

But that gauge can not be too small, or the BMS will trip too early in case of large charge / discharge currents, due to the cells within a 1S pool not being at the same voltage anymore.

So what to do ?

Well, hang on, this now raises again the question of whether the same side or the midpoint strategies from the previous post Best Wiring Strategy for Battery Packs ? would behave the same ? Or could they now be a better option ?

Same side wiring:

with 0.4mΩ R1s: Max= 80A, Min= 28A, settling time: 4.7 hours

Midpoint:

with 0.4mΩ R1s: Max= 67A, Min= 41A, settling time: 2.4 hours

Oh boy, this is getting messy... Same side wiring is still the worst but midpoint is now looking better than opposite corners !

Summary with various R1s values:

Conclusions:

For these wiring strategies R1s interconnects create notable current imbalances that can be even higher than the nominal 50A current draw per string...
Depending on the R1s value a wiring strategy can be better or worse than another
Opposite corners can deliver the best results but only with high R1s values, unacceptable for BMS monitoring

La soggy baguette de Walmart, results are all over the place !

Indeed, that's because these large and contradictory trends point to a high sensitivity from these topologies to the R1s parameter. Leading to large variations in results.

This is not a good sign if a user expects a predictable, repeatable and reliable pack performance over many years. Small interconnect variations over time will happen, so they could notably throw the currents out of balance and accelerate aging of some cells over others.

A battery pack, especially in mobile applications, should be "Build and forget" with not much need for regular inspection, maintenance, etc. Peace of mind, predictable performance and longevity are key priorities.

So what to do ?

Easy, use a star wiring strategy:

It can be done the quick way 😅

Or more professionally by using a B+ and a B- busbar to which each string connects.

Some key considerations must be followed, though:

the busbars must be very beefy, sized or even oversized for the max total current of the application (250A for this van)
all the interconnects from the busbars to the strings must be built the same and have the same length
the main B+ and B- wires must be connected to a post in the middle of their busbar

The star topology avoids the current path asymmetries inherent to connecting the main wiring directly, or close, to a cell's terminal post. No current imbalance occurs anymore, no matter the R1s value:

R1s = 0.4mΩ

Actually, even if one of the R1s interconnects is out of whack no current imbalance ensues. Because the series R paths are still the same between strings. Replace only one of the 0.4mΩ R1s interconnects by 0.15mΩ or 1mΩ, or even remove it, and you get the same perfect current graph as above.

This said, the busbars will still introduce a few 0.01mΩ of difference between their posts and, consequently, between the strings. So let's throw off one of the main series Rp interconnects to get a sense of the impact. Say, from 0.15mΩ to a high 0.25mΩ on only 1 string:

Max= 52A, Min=45A
Settling time: 3.3hours

Excellent ! A small response to large perturbations is the signature of a stable and resilient system. It should therefore exhibit a predictable, repeatable and reliable behavior, making our pack much more "Build and forget".

And finally, there we have it, the star wiring is the: